A new set of patches submitted to the QEMU development mailing list provides the first detailed look at AMD’s upcoming Zen 6 server architecture. Posted by AMD software engineer Ben Cheatham on June 30, 2026, the four-patch series introduces an official “Epyc-Venice” CPU model into the project’s x86 emulation code. An independent lscpu output from an engineering sample, shared via OpenBenchmarking, aligns exactly with the patch’s specifications, confirming the data against real silicon.
CPU Identification and Instruction Set Expansions
The Venice processor is defined under family 26, model 80, stepping 0, and presents itself to guest operating systems as “AMD EPYC-Venice Processor.” It extends the feature baseline established by the previous Epyc-Turin (Zen 5) model and adds a suite of new instruction sets. These include AVX512 FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, and a fresh AVX512 Bit Matrix Multiply (BMM) instruction, which was introduced earlier within the same patch series. The model also activates CET Shadow Stack support, TSC_ADJUST, and a new speculative-execution mitigation called Enhanced Return Address Prediction Security (ERAPS).
A key architectural detail is the SRSO_NO flag, which indicates the core is not vulnerable to Speculative Return Stack Overflow. This class of flaw, which previously affected earlier Zen generations, exploits the CPU’s return address predictor to trick it into speculatively executing code at an attacker-controlled address before the misprediction is corrected. Older AMD chips have relied on software-level mitigations, such as flushing branch prediction state during context switches, an approach that carries a measurable performance cost. By closing this attack path in silicon rather than through software patching, Venice removes that overhead. The hardware mitigation is paired with ERAPS, which manages how much return address history the predictor tracks per guest, governed by the RAPSIZE parameter discussed in the same series. Similar vulnerabilities involving hardware branch prediction have been a long-standing concern across the industry, with Intel processors also requiring patches that affect performance.
Cache Hierarchy Details
The patch maintains the same per-core L1 cache dimensions seen in the Turin generation: a 48 KB, 12-way L1 data cache and a 32 KB, 8-way L1 instruction cache. The L2 cache remains at 1 MB per core, 16-way and inclusive, also unchanged from Zen 5. At the die level, L3 cache is listed at 64 MB with 16-way associativity, and this figure is independently corroborated by the OpenBenchmarking engineering sample data.
Neither the patch series nor the public benchmarking output specifies memory support or pricing. However, AMD CTO Mark Papermaster has separately confirmed that Epyc Venice will be formally introduced at the company’s Advancing AI event in San Francisco on July 22 and 23, meaning full specifications, pricing, and availability are expected within days.
Sources: lore.kernel.org, openbenchmarking.org