A new wave of internal documentation has shed light on Qualcomm’s upcoming flagship mobile platform, known internally as SM8975 and widely expected to be marketed as the Snapdragon 8 Elite Gen 6 Pro. The chip appears poised to deliver one of the most significant architectural overhauls in the company’s recent history, touching everything from transistor density and graphics capabilities to modem design and wireless connectivity.
Silicon Footprint and Manufacturing Economics
Physical analysis, calibrated against official package dimensions of 21.2 × 14 mm with a margin of roughly 1%, places the SM8975 die at approximately 12.6 × 10.67 mm, yielding an area of about 134 mm². That figure stands larger than the 126.2 mm² die footprint of the current Snapdragon 8 Elite Gen 5, even as the new part migrates to a more advanced fabrication node. The increase suggests that architectural expansion has outpaced the density improvements of the process shrink. For comparison, MediaTek’s Dimensity 9500 measures around 140 mm², indicating that Qualcomm’s transition to a 2 nm-class node is still delivering tangible efficiency headroom despite integrating additional Matrix arithmetic logic units and enlarged cache structures.
Translating the die size into a cost estimate using industry-standard wafer-yield modeling—assuming a 300 mm wafer, a defect density of 0.1 defects per square centimeter, and a projected wafer price of $33,000 on TSMC’s N2P node—produces a raw silicon cost of roughly $84.62 per good die. This figure excludes packaging, testing, binning, and IP licensing fees, and should be read as a directional indicator of upward cost pressure rather than a confirmed bill-of-materials component.
Process Node and CPU Configuration
SM8975 is reported to be built on TSMC’s N2P process, an enhanced 2 nm-class node that marks Qualcomm’s first move beyond 3 nm for a flagship system-on-chip. That positions it a full node ahead of the Snapdragon 8 Elite Gen 5’s N3P manufacturing and slightly ahead of the Apple A20 Pro, which is expected to use the baseline N2 process.
The CPU complex adopts a 2+3+3 layout within Qualcomm’s custom Oryon architecture: two prime cores, three performance cores, and three efficiency cores. While unofficial sources have floated a peak clock speed near 4.8 GHz, such figures remain unverified in any documentation reviewed so far and should be treated as speculative for the time being.
Adreno 850 Graphics and AI-Focused Matrix Hardware
The Pro-tier silicon pairs with the new Adreno 850 GPU, succeeding the Adreno 840 found in the outgoing SM8850 generation. Graphics memory stays flat at 18 MB, matching the prior flagship rather than scaling upward. The driver stack introduces a more granular dynamic clock and voltage scaling implementation that provides additional frequency steps, improved jank detection and feedback, and better responsiveness when multiple GPU contexts run concurrently. The supported API surface remains unchanged—OpenGL ES up to 3.2, OpenCL 3.0 FP, EGL 1.5, and Vulkan 1.4—keeping OEM driver-migration work minimal.
A clear segmentation strategy emerges when comparing the Pro chip with the standard SM8950 variant, which is expected to ship with a scaled-down Adreno 845 and 12 MB of graphics memory.
For the first time, the GPU’s shader processor incorporates two dedicated Matrix ALU blocks purpose-built to accelerate general matrix multiply and convolution operations, the mathematical backbone of on-device AI workloads. These blocks enable a feature called AI Frame Fusion, Qualcomm’s approach to AI-driven upscaling and frame interpolation. Both the Matrix ALU blocks and AI Frame Fusion appear exclusive to the Adreno 850 inside the SM8975; the Adreno 845 in the standard SM8950 reportedly omits them, reinforcing the Pro tier’s feature differentiation.
How AI Frame Fusion Works
AI Frame Fusion operates across two distinct modes. A super-resolution mode combines motion vectors, a depth buffer, a low-resolution color buffer, and the previously rendered frame to upscale output to 1080p or 1440p. A separate frame-generation mode relies on motion-vector and optical-flow reprojection across consecutive frames to interpolate an entirely new frame between them, targeting higher perceived frame rates without a proportional increase in power consumption. Both modes leverage the new Matrix ALUs alongside the GPU’s on-chip graphics memory pool to improve efficiency.
Memory, Modem, and Wireless Connectivity
The SM8975 is reported to feature a shared 16 MB L2 cache and an 8 MB system-level cache, representing a meaningful increase over the current generation’s configuration. On the memory side, the Pro variant supports both LPDDR5X and the emerging LPDDR6 standard, whereas the standard SM8950 is limited to LPDDR5X. That segmentation likely reflects the pricing environment for LPDDR6 amid ongoing tightness in the DRAM supply chain.
Modem duties fall to Qualcomm’s new X105 baseband, a part that has not previously appeared in a shipping Snapdragon platform. Both the Pro and standard variants are said to share the same RF front end, which is reportedly not backward-compatible with older modems, suggesting the base SM8950 will also carry the X105, possibly in a cut-down configuration.
Two companion FastConnect 8800 chips handle wireless connectivity. The WCN8841 and WCN8851 both support Wi-Fi 8 in a 2×2, 300 MHz MIMO setup, along with Bluetooth HDT on the 2.4 GHz band and Thread. The higher-tier WCN8851 adds Bluetooth 7.0, a second Wi-Fi radio path capable of 2×4 or 4×4 MIMO at 320 MHz, Bluetooth 7.0 operation on the 5 GHz and 6 GHz bands, and ultra-wideband.
On the modem-RF side, two transceivers accompany this generation. The SDR765 is a sub-6 GHz-only component manufactured on TSMC’s N6RF node—a shift away from Samsung’s earlier 14 nm RF process that aligns with the RF node used in the Apple C1 system. It supports 2×2 MIMO uplink, 4×4 MIMO downlink, 1024-QAM modulation, and the n253, n255, and n256 satellite bands. The SDR885 marks a more substantial leap: it is Qualcomm’s first sub-6 GHz transceiver to deliver simultaneous 4×4 MIMO on both uplink and downlink, enabling upload throughput that can match download performance for the first time on a Snapdragon platform. It supports 256-QAM uplink, 1024-QAM downlink, sub-6 GHz and mmWave operation under 3GPP Release 18, with 20 transmit ports arranged in a 7+7+3+3 configuration and 16 primary plus 16 diversity receive-input paths.
Pricing Strategy and Launch Timeline
Qualcomm’s approach this generation appears to split the flagship tier more sharply than in previous cycles. The SM8975 is expected to carry substantially higher production costs than the standard SM8950, a gap likely widened further by LPDDR6 pricing, and the Pro silicon may be reserved for a smaller set of ultra-premium devices rather than spanning the entire flagship lineup. Industry estimates of significantly elevated platform pricing usually capture the complete cost that OEMs pay, encompassing the SoC, RF transceivers, and FastConnect wireless chip bundled together—meaning they should not be directly compared to the roughly $84.62-per-die raw silicon figure.
The Snapdragon 8 Elite Gen 6 family is expected to debut at Qualcomm’s Snapdragon Summit, officially confirmed for September 22 through September 24, 2026, in Maui, Hawaii. Xiaomi is widely tipped to be first to market with a device powered by the new platform, potentially unveiling the Xiaomi 18 series in China alongside Qualcomm’s keynote. Commercial availability from other manufacturers is anticipated later in the year and into early 2027.
Source: semianalysis.com