Tag: JEDEC

  • UFS 5.0 Storage at 10.8 Gbps: Speed Close to PCIe 5.0 SSDs

    UFS 5.0 Storage at 10.8 Gbps: Speed Close to PCIe 5.0 SSDs

    Key Takeaways

    1. JEDEC has been standardizing flash memory since 2011, focusing on Universal Flash Storage (UFS) for smartphones and tablets.
    2. UFS 4.0, introduced in 2022, offers transfer speeds of up to 5,800 Mbps using two lanes, with UFS 5.0 promising even higher speeds of 10,800 Mbps.
    3. While UFS 5.0 narrows the speed gap with top PCIe SSDs, smartphones still lag behind the fastest laptops in terms of storage speed.
    4. UFS 5.0 is expected to be more reliable and easier to integrate into devices, featuring improvements in signal integrity and enhanced security.
    5. Real-world performance of UFS 5.0 may vary, as seen with UFS 4.0 devices that do not always achieve their maximum potential speeds.

    Since 2011, the JEDEC industry group has been working on standardizing flash memory for gadgets such as smartphones and tablets, which depend on Universal Flash Storage (UFS) rather than PCIe. UFS 4.0 was introduced in 2022, boasting transfer speeds of 2,900 Mbps on a single lane and 5,800 Mbps when using two lanes. Now, UFS 5.0 is almost complete and is expected to deliver even greater speeds.

    New Speed Expectations

    JEDEC has announced a peak speed of 10,800 Mbps for UFS 5.0. To put this into perspective, top-tier PCIe 5.0 SSDs, like the Samsung 9100 Pro (starting at $128 on Amazon), can reach around 14,700 Mbps. Although smartphones are still behind the quickest laptops, the difference is narrowing. JEDEC emphasizes that this enhanced storage capability will be essential to satisfy the increasing needs of AI applications.

    Reliability and Integration

    UFS 5.0 is anticipated to be more dependable due to improvements in signal integrity. It is also designed to be simpler to incorporate into devices thanks to a distinct power supply for the signaling unit and storage subsystem, while inline hashing bolsters security. As has been the case in the past, it may take a few years for this new UFS standard to become widely available, and even then, UFS 5.0 does not assure faster storage speeds. For instance, the Google Pixel 10 Pro with 256GB of storage or more uses UFS 4.0, but in our detailed assessment, the smartphone only achieved relatively low data rates of up to 1,492 Mbps, while rival devices typically perform more than twice as fast.

    Conclusion

    Overall, the advancements in UFS technology show promise for the future of mobile devices, but consumers should remain cautious as real-world performance can vary significantly.

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  • JEDEC Unveils LPDDR6 Standard with 14,400 MT/s Data Rates

    JEDEC Unveils LPDDR6 Standard with 14,400 MT/s Data Rates

    Key Takeaways

    1. Launch of LPDDR6 Standard: JEDEC has introduced JESD209-6, marking the official launch of LPDDR6 five years after DDR5.

    2. Enhanced Performance: LPDDR6 features dual-sub-channel architecture, increasing peak data rates to 10,667 – 14,400 MT/s, providing bandwidths of 28.5 – 38.4 GB/s.

    3. Improved Power Efficiency: The standard reduces power consumption through lower core voltages, Dynamic Voltage Frequency Scaling, and partial self-refresh capabilities.

    4. Increased Reliability: LPDDR6 includes on-die ECC, programmable link protection, and built-in self-test features to enhance fault coverage and reliability for critical applications.

    5. Industry Support and Adoption: Major chipmakers and tech companies, including Qualcomm and Samsung, are backing LPDDR6, indicating rapid adoption across various devices.

    JEDEC has introduced JESD209-6, marking the official launch of LPDDR6, five years after DDR5 made its debut in the market. This new standard enhances peak data rates to between 10,667 and 14,400 MT/s, which translates to bandwidths of about 28.5 to 38.4 GB/s. It also aims to meet the lower power requirements that are critical for mobile devices and next-gen AI technologies.

    Enhanced Performance Features

    The performance improvements stem from a dual-sub-channel architecture. Each memory die includes a 24-bit channel, which is further divided into two 12-bit sub-channels. This setup reduces access times, decreases latency, and keeps a minimum granularity of 32 bytes. Additionally, the capability for on-the-fly burst-length control enables easy transitions between 32 and 64-byte data transfers.

    Better Power Efficiency

    Power efficiency sees enhancements due to lowered core voltages and Dynamic Voltage Frequency Scaling for Low Power, which lowers supply voltages during lighter workloads. The introduction of static and dynamic efficiency settings helps minimize active circuitry when demand is low. Furthermore, the design allows for partial self-refresh to lower standby power usage.

    Improved Reliability Features

    Advancements in reliability come from on-die ECC, programmable link protection, per-row activation counting, and designated meta regions for priority tasks. Additional features like optional command/address parity and built-in self-test capabilities boost fault coverage, fulfilling the more stringent needs of both automotive and data-center applications.

    The industry’s reaction has been immediate. A variety of chipmakers, IP vendors, and suppliers of testing equipment—such as Cadence, Synopsys, MediaTek, Qualcomm, Samsung, Micron, and SK Hynix—have expressed their support, indicating a quick shift towards adoption in smartphones, personal computers, edge servers, and automotive systems.

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