AMD Zen 6 CPUs Expected with Up to 96MB L3 Cache on Non-X3D Model

Key Takeaways

1. The upcoming AMD Zen 6 processors may feature a high-end desktop variant with up to 24 CPU cores, surpassing the previous limit of 16 cores.
2. AMD plans to increase the L3 cache per CCD to 48 MB, potentially resulting in up to 224 MB of L3 cache for a 24-core CPU with dual V-cache.
3. A single CCD may house 16 Zen 6 cores, with configurations available for 32-core variants totaling 128 MB of L3 cache.
4. Future laptop models might combine Zen 5 and Zen 6 CCDs, as suggested by the Strix Point development.
5. The next-generation Epyc server processors are expected to benefit from the increased cache and new core configurations.

Now that the AMD Zen 5 series is largely released, the whispers about the upcoming Zen 6 processors are becoming more common. Initially, it appears that the highest-end desktop variant (possibly named Ryzen 9 11,950X) will surpass the previous limit of 16 CPU cores. A previous leak hinted that this number might reach up to 24 cores. A recent report from Weibo provides further details on this topic.

Increased Cache Capabilities

AMD is set to boost the L3 cache per CCD to 48 MB. Therefore, a 24-core CPU utilizing 2 Zen 6 CCDs would feature a total of 96 MB of L3 cache. If a 64 MB 3D V-cache tile is added to one of the CCDs, this would result in 160 MB of L3 cache, and if both CCDs have one, that would be an impressive 224 MB. However, it’s still too early to make guesses about what the Zen 6 X3D will offer, though it would be a perfect opportunity to introduce a dual V-cache CPU for consumers.

New Core Configurations

Additionally, AMD intends to fit 16 Zen 6 cores within a single CCD, accompanied by 64 MB of L3 cache. There is a 32-core variant with 2 of these CCDs totaling 128 MB of L3 cache, though it remains unclear which lineup it belongs to. If Strix Point is indicative of future developments, some laptop models may feature a combination of Zen 5 and Zen 6 CCDs. Also, this configuration is expected to appear in the next-generation Epyc server processors, which will also gain from the increased cache.

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